Author : Naresh Kumar Gedam, Prof. Rajeev Thakur [ Volume No.:IX, Issue No.II-Mar 2020] [Page No : 936-941] [2020]

The need for low power integrated circuits is well known because of their extensive use in the portable electronic equipments. On-chip SRAMs (Static Random Access Memory) determine the power dissipation of SoCs (System on Chips) in addition to its speed of operation. Hence it is essential to have energy-efficient SRAMs—Static Random Access Memories (SRAMs) which focuses on optimizing delay and power. Static Random Access Memory (SRAM) continues to be a critical component across a wide range of microelectronics applications from consumer wireless to high-performance processors, multimedia and System on Chip (SoC) applications, the leakage power of Static Random Access Memory (SRAM) is becoming one of the most critical concerns for low power applications and CMOS SRAM cell consumes very less energy and have less read and write time. In a review on 6T SRAM cell, 9T SRAM cell, 10T SRAM cell configurations are compared to our proposed SRAM circuit based on low power consumption. This learning paper plans to provide an Energy Efficient Low Power SRAM Cell, and here various techniques and approaches are discussed to achieve better performance.